• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The invention relates to an integrated circuit (1), comprising: a field effect transistor (2), comprising: first and second conduction electrodes (201, 202); a channel region (203) disposed between the first and second conduction electrodes; a gate stack (220) disposed vertically above the channel region, and comprising a gate electrode (222); a RRAM type memory point (31) arranged under the channel zone, or formed in the gate stack under the gate electrode.
    公开号:FR3045938A1
    申请号:FR1563063
    申请日:2015-12-22
    公开日:2017-06-23
    发明作者:Laurent Grenouillet；Sotiris Athanasiou；Philippe Galy
    申请人:Commissariat a lEnergie Atomique CEA；STMicroelectronics SA；STMicroelectronics Crolles 2 SAS；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    The invention relates to RRAM memories, and in particular cointegration of such memories with field effect transistors.
    In order to overcome the limitations in terms of miniaturization, power consumption and manufacturing complexity of non-volatile floating gate memory technologies, the semiconductor industry is developing different alternative technologies. Among alternative nonvolatile memory technologies under development, RRAM type memories are of technical interest.
    The RRAM type memories are based on the formation and reversible breaking of a conductive filament: a dielectric material, which is normally insulating, may be forced to be conductive through a filament or conduction path after the application of a sufficiently high voltage. Once the filament is formed, it can be reset or programmed by an appropriately applied voltage.
    In the particular case of OxRAM memories, the conductive filament is made from oxygen vacancies in an insulating material based on metal oxide. The OXRAM memories have a very good thermal stability, theoretically allowing to keep the information reliably for several years at high temperature, with a lifetime of a very large number of programming / deprogramming cycles and / or reading.
    An OxRAM memory cell can be produced from a base memory point according to three known solutions.
    In a first approach, the simplest, the memory point can be used as a basic memory cell, and used in a configuration in which parallel bit lines are traversed by perpendicular word lines, with the switching material placed between the word line and the bit line at each crossing point. This configuration is called a cross point cell. Since this architecture can lead to a large parasitic current flowing through unselected memory cells from neighboring cells, the cross point matrix can have very slow read access.
    In a second approach, a selection element may be added to eliminate this parasitic current, but this selection element induces an electrical over-consumption.
    In a third approach, a field effect transistor is added, facilitating the selection of a memory point and thus optimizing the access time, while limiting the current flowing in the cell, thus avoiding transient overcurrents that can alter or even destroy the cell.
    In this third approach, the integration density is however strongly altered, the selection transistors occupying a significant surface of the integrated circuit substrate. Furthermore, the interconnections between the memory points and the selection transistors induce a certain complexity of the manufacturing process of the integrated circuit.
    The document 'Scalable Higlhy Non-volatible Resistive Memory using Simple Binary Oxide Driven by Asymmetric Unipolar Voltage Pulses' by I.G. Baek et alias, published by ΓΙΕΕΕ in 2004, describes an example of cointegration of OxRAM memory cells with selection transistors. In order to improve the integration density of the integrated circuit, this document proposes to integrate the selection transistors in a pre-metallization layer or FEOL layer, and to integrate the OXRAM memory points in a layer after metallization. or BEOL layer, in line with the selection transistors.
    Such a structure has a limited integration density. Such a structure is otherwise unsuitable for protecting memory points against electrostatic discharges. Moreover, the design of memory point arrays in practice poses problems of access time to the memory points and it is difficult to discriminate the programming states of different memory points for matrices of large memory points, the reading of the resistance value of the memory point not to be affected by an access resistor of the same order of magnitude.
    Moreover, there is a constant need to have field effect transistors whose threshold voltage can be adapted. High threshold voltage field effect transistors are generally favored for power applications to limit the power consumption of the transistor in the off state. Low threshold voltage field effect transistors are generally favored for logic applications, in order to obtain an optimal switching speed. In practice, it is often necessary to be able to modify or adapt the threshold voltage of a transistor during the life cycle of the integrated circuit. The invention aims to solve one or more of these disadvantages. The invention thus relates to an integrated circuit, comprising: a field effect transistor, comprising: first and second conduction electrodes; a channel zone disposed between the first and second conduction electrodes; a gate stack disposed vertically above the channel zone, and comprising a gate electrode; a memory point of type RRAM arranged under the channel zone, or formed in the gate stack under the gate electrode. The invention also relates to the following variants. Those skilled in the art will understand that each of the features of the following variants may be independently combined with the above features, without necessarily constituting an intermediate generalization.
    According to a variant, the integrated circuit comprises a programming circuit configured to selectively create or remove a conductive filament in said memory point.
    According to one variant, said memory point is of the OxRAM type.
    According to another variant, said memory point is formed in the gate stack.
    According to another variant said memory point comprises a first electrode in electrical contact with the gate electrode, and comprises an insulator in contact with the first electrode and configured for the selective formation of a conductive filament.
    According to yet another variant, said transistor is of the FDSOI type, the channel zone of said transistor having a zone including a dopant implantation, said programming circuit being configured to apply a potential difference between said first electrode of the memory point and said zone. including the implantation of dopants so as to form a conductive filament in the insulator.
    According to one variant, said insulator of the memory point is a gate insulator in contact with the channel zone.
    According to another variant: said memory point comprises a first electrode in electrical contact with the gate electrode, and comprises an insulator in contact with the first electrode and configured for the selective formation of a conductive filament; said programmable circuit is configured to apply a potential difference between said first electrode of the memory point and the first and / or second conduction electrode of the transistor so as to form a conductive filament in the insulator.
    According to another variant: said transistor comprises a gate insulator in contact with the channel zone; said memory point comprises: a first electrode in electrical contact with the gate electrode; an insulator in contact with the first electrode and configured for the selective formation of a conductive filament; a second electrode formed in contact with said gate insulator, separated from said first electrode via the insulator of the memory point; said programming circuit is configured to apply a potential difference between said first electrode of the memory point and the second electrode of the memory point so as to form a conductive filament in the insulator.
    According to yet another variant, said transistor is of the SOI type and in which the memory point is arranged under the channel zone.
    According to a variant, said memory point comprises: a first electrode formed in a semiconductor substrate directly above the channel zone; an insulator in contact with the first electrode, separating the first electrode from the channel zone, and configured for the selective formation of a conductive filament.
    According to another variant, said programming circuit is configured to apply a potential difference between said first electrode of the memory point and the first and / or second conduction electrode of the transistor so as to form a conductive filament in the insulator.
    According to another variant: the channel zone of said transistor has a zone including a dopant implantation; said programming circuit is configured to apply a potential difference between said first electrode of the memory point and said zone including the implantation of dopants so as to form a conductive filament in the insulator.
    According to yet another variant, said memory point comprises: at least two electrodes formed in a semiconductor substrate under the channel zone; an insulator in contact with said at least two electrodes, separating the channel zone and said at least two electrodes formed in the semiconductor substrate, and configured for the selective formation of a conductive filament.
    According to a variant, said first electrode is formed in a metal selected from the group comprising Ti, TiN and TaN.
    According to another variant, said insulator is formed in a material chosen from the group comprising HfCte, HfSiON or HfAIO. Other features and advantages of the invention will emerge clearly from the description which is given below, by way of indication and in no way limiting, with reference to the accompanying drawings, in which: FIG. 1 is a diagrammatic sectional view of FIG. an example of RRAM memory point; FIG. 2 is a diagrammatic sectional view of a first embodiment of an integrated circuit according to the invention, including a field effect transistor and a memory point of the RRAM type; FIG. 3 is a diagrammatic sectional view of a second embodiment of an integrated circuit according to the invention; FIG. 4 is a diagrammatic sectional view of a third embodiment of an integrated circuit according to the invention; FIG. 5 is a diagrammatic sectional view of a fourth embodiment of an integrated circuit according to the invention; FIG. 6 is a diagrammatic sectional view of a fifth embodiment of an integrated circuit according to the invention; FIG. 7 is a diagrammatic sectional view of a sixth embodiment of an integrated circuit according to the invention; FIG 8 is a schematic sectional view of a seventh embodiment of an integrated circuit according to the invention; FIG 9 is a schematic sectional view of an eighth embodiment of an integrated circuit according to the invention; FIG. 10 is a diagrammatic sectional view of a ninth embodiment of an integrated circuit according to the invention; FIG 11 is a schematic sectional view of a tenth embodiment of an integrated circuit according to the invention; FIG. 12 is a diagrammatic sectional view of an eleventh embodiment of an integrated circuit according to the invention; FIG. 13 is a diagrammatic sectional view of a twelfth embodiment of an integrated circuit according to the invention.
    FIG. 1 is a diagrammatic sectional view of an exemplary memory point 8 of RRAM type (for Resistive Random Access memory in English language), in particular of OxRAM type (for Oxide-based Resistive Memory in English language). The memory point 8 of the OxRAM type comprises a metal upper electrode 81, a metal lower electrode 82, and a dielectric 83 interposed between the upper electrode 81 and the lower electrode 82. The dielectric 83 is made selectively conductive by application of a appropriate potential difference between the upper electrode 81 and the lower electrode 82. Such a programming potential difference is for example applied by a control circuit 90. A conductive filament 84 is then formed in the dielectric 83, the memory point 8 being then in a programmed state in which it has a reduced electrical resistance between the electrodes 81 and 82. This programmed state is maintained even in the absence of supply of the memory point 8. By the application of another difference of potential through the control circuit 90, it is possible to de-program the memory point 8 and the filament 84. By subsequently applying a read potential difference between the electrodes 81 and 82, the control circuit 90 can measure the current passing through the memory point 8 to determine whether it is in the programmed state or deprogrammed. In general, for an OxRAM type of memory, the dielectric 83 includes a binary transition metal oxide. Such a dielectric 83 is intended to allow metal to migrate electrodes 81 and 82 to form the conductive filament 84 in the programmed state.
    An integrated circuit is proposed, cointegrating a RRAM type memory point in a field effect transistor, either in the gate stack of this transistor or in line with the channel region of this transistor.
    An integrated circuit is thus obtained with a field effect transistor cointegrated with a RRAM memory point, with a very great compactness. In addition, such an integrated circuit can be obtained with standardized steps of manufacturing processes. Such cointegration is very stable at high temperature. Such an integrated circuit also makes it possible to modulate the threshold voltage of the transistor in a simple manner and with a considerable amplitude.
    Some variants are particularly compatible with protection against electrostatic discharge. In general, the protection of a memory point present in the pre-metallization layer is much easier to protect against electrostatic discharges than a memory point according to the state of the art present in metallization layers. The immunity against electrostatic discharges is particularly improved for discharges of the type CDM (Charged Device Model in English) very difficult to control.
    In the first to ninth embodiments of integrated circuits 1, as well as in the twelfth embodiment, a memory point of the RRAM type is formed in a gate stack 220 of a field effect transistor 2 of each of these modes. of realization.
    In the tenth to twelfth embodiments of integrated circuits 1, a memory point is provided under a channel zone 203 of the field effect transistor 2 of each of these embodiments.
    FIG. 2 is a diagrammatic sectional view of an integrated circuit 1 including a field effect transistor 2 and a memory point 31 of the RRAM type, according to a first embodiment. The field effect transistor 2 is formed on a semiconductor substrate 100, typically made of silicon, for example silicon having a low p-type doping. The substrate 100 is here of massive type (for bulk in the English language). The field effect transistor 2 comprises an active layer of semiconductor material formed on the substrate 100. The active layer includes a source region 201, a drain region 202, and a channel region or region 203 formed between the source 201 and the drain 202.
    A gate stack 220 is formed vertically above the channel zone 203. The gate stack 220 comprises a gate insulator 223 formed on the channel zone 203. A RRAM memory point 3 is disposed on the gate 223. An electrode or a metal gate region 222 is disposed on the memory point 31. A contact layer 221 (typically a silicide) is disposed on the gate electrode 222 to provide its connection. Electrical insulating spacers 231 and 232 are formed on the edges of the gate stack 220. The spacers 231, 232 cover the flanks of the gate insulator 223, the memory point 31, the gate electrode 222 and the layer The spacers 231, 232 electrically isolate the gate electrode 222 and the memory point 31 from the source and drain contacts 211 and 212, respectively. The electrical contacts 211 and 212 are formed in contact respectively with the drain 201 and the source 202. The electrical contacts 211 and 212 are arranged on either side of the gate stack 220.
    The memory point 31 comprises a non-illustrated upper electrode in electrical contact with the gate electrode 222. A non-illustrated dielectric is interposed between the upper electrode and the gate insulator 223. The structure of the memory point 31, in particular its materials, their thicknesses and differences in programming potential / deprogramming, are known per se to those skilled in the art. More specific examples will be developed later.
    The integrated circuit 1 comprises a control circuit 91, configured to program or deprogram the memory point 31. The combination of the memory point 31 and the field effect transistor 2 can be used: -that is to modulate the threshold voltage of the transistor 2 by means of the programming state of the memory point 31. This modulation can also be used for cointegrated transistors, intrinsically having different levels of threshold voltages (for example so-called low-Vt, Hight-Vt or Standard-transistor transistors). Vt in the publications); or to allow reading of the programming state of the memory point 31 via the transistor 2. In this case, the memory point 31 in the programmed state (comprising a conductive filament) can correspond to a level logic 1, while the memory point 31 in the deprogrammed state can correspond to a logical level 0.
    In order to form the conductive filament and thus to program the memory point 31, the control circuit 91 applies a suitable programming potential difference between its upper electrode on the one hand and the source 211 and / or drain contact on the other hand. 212, and / or a contact of the substrate 100. A potential is for example applied to the upper electrode via the gate electrode 222 with which it is in electrical contact.
    To suppress the conductive filament and thus deprogram the memory point 31, the control circuit 91 applies an appropriate deprogramming potential difference between its upper electrode on the one hand and the source contact 211 and / or on the other hand drain 212. The difference in deprogramming potential is of opposite polarity to that of the programming potential difference. The difference in deprogramming potential may be of the same order of magnitude as the programming potential difference.
    When the memory point 31 is used to modulate the threshold voltage of the transistor 2, its programming / deprogramming state makes it possible to modulate the electric field generated by the gate electrode 202 on the channel zone 203, for a given potential difference. between the source 201 and this gate electrode 222. When the memory point 31 is in the programmed state, the voltage applied to the gate electrode 202 can be applied as close as possible to the gate insulator 223 via of the conductive filament formed. The field applied on the channel zone 203 is then maximal. When the memory point 31 is in the deprogrammed state, the electric field applied to the channel zone 203 is generated at the gate electrode 202. The field applied to the channel zone 203 thus has a smaller amplitude than when the memory point 31 is in the programmed state. The threshold voltage of the transistor 2 is thus increased when the memory point is in the deprogrammed state. The control circuit 91 can thus be configured to program / deprogram the memory point 31, and to apply different gate potentials in order to make the transistor 2 turn on, depending on the programming state of the memory point 31. The memory point 31 will be dimensioned so that the programming potential / deprogramming differences have a much greater amplitude than the threshold voltage of the transistor 2, so that a command making the transistor 2 passes does not induce the programming or the deprogramming of the memory point 31 .
    When the memory point 31 is used to memorize a logic state and allow its subsequent reading, the reading of this logic state is performed via the transistor 2. The control circuit 91 can apply a potential difference between the gate and the gate. source 201 and measure the corresponding current between the source and the drain. This potential difference is for example greater than the threshold voltage when the memory point 31 is in the programmed state, and lower than the threshold voltage when the memory point 31 is in the deprogrammed state. Measuring the current between the source and the drain thus makes it possible to determine the programming state of the memory point 31.
    Conclusive tests were carried out with a layer of insulator 223 in S1O2 with a thickness of 1 nm, and a layer of insulator of the memory point 31 in HfO2 having a thickness of 1.5 nm.
    Figure 3 is a schematic sectional view of an integrated circuit 1 according to a second embodiment. The integrated circuit 1 according to this second embodiment differs from that of the first embodiment only by the structure of the gate electrode. The gate electrode of the integrated circuit 1 of the first embodiment is here replaced by a gate electrode 224 in conductive polysilicon. It is also conceivable to use a gate electrode combining a metal layer and a polysilicon layer.
    The programming / deprogramming of the memory point 32, the switching of the transistor 2 and / or the reading of the programming state of the memory point 32 can be performed as detailed with reference to the first embodiment.
    Figure 4 is a schematic sectional view of an integrated circuit 1 according to a third embodiment. The integrated circuit 1 according to this third embodiment comprises a gate stack 220, whose structure is identical to that of the integrated circuit 1 of the second embodiment. The source 201, the drain 202, and the contacts 211 and 212 have a structure identical to that of the integrated circuits of the first and second embodiments. The field effect transistor 2 is here provided on a buried insulating layer 120. The active semiconductor layer of the field effect transistor 2 is thus electrically isolated from the substrate 100 via the insulating layer 120. The buried insulating layer 120 may for example be of UTBOX type (for Ultra Thin Burried Oxide in English language) and typically have a thickness of between 10 and 50 nanometers. The buried insulating layer 120 may for example be made in a manner known per se in S102.
    Transistor 2 is here of type FDSOI (for Fully Depleted Silicon On Insulator in English language). A zone 241 comprising a dopant implantation is formed in the channel zone 203, directly above the gate stack 220. The zone 241 of the illustrated example is distant from the interface between the channel zone 203 and the gate insulator 223. The zone 241 can selectively be biased through the control circuit 91, for example by means of an electrical contact with the channel zone 203.
    The zone 241 is used by the control circuit 91 to implement the programming or the deprogramming of the memory point 33. In order to form the conductive filament and thus to program the memory point 33, the control circuit 91 applies a programming potential difference. between the upper electrode on the one hand and the zone 241 on the other hand. The control circuit 91 can also apply a suitable programming potential difference between its upper electrode on the one hand and the substrate on the other hand. 100. A potential is for example applied to the upper electrode via the gate electrode 224 with which it is in electrical contact.
    To suppress the conductive filament and thus to deprogram the memory point 33, the control circuit 91 applies an appropriate deprogramming potential difference between its upper electrode on the one hand and the zone 241 on the other hand. The control circuit 91 It can also apply an appropriate deprogramming potential difference between its upper electrode on the one hand, and the substrate 100 on the other hand. The difference in deprogramming potential is of opposite polarity to that of the programming potential difference.
    Depending on the programming state of the memory point 33, it is possible to obtain a modulation of the threshold voltage of the transistor 2 or a reading of the programming state of this memory point 33, as for the first embodiment.
    In the third illustrated embodiment, the transistor 2 advantageously comprises a rear gate 110 (frequently referred to as Back Gate in English language), formed in the substrate 100, under the buried insulating layer 120. The rear gate 110 presents in a manner known per se, an N or P doping with a concentration much higher than that of the substrate 100. Combined with a UTBOX type layer 120, such a rear gate 110 makes it possible to modify the threshold voltage of the transistor 2. The gate rear 110 may be biased through the control circuit 91, in order to further modify, in known manner, the threshold voltage of the transistor 2.
    Figure 5 is a schematic sectional view of an integrated circuit 1 according to a fourth embodiment. The integrated circuit 1 according to this fourth embodiment is identical to that of the third embodiment, but details an example of structure of the memory point 34. In the embodiment of Figure 5, the memory point 34 comprises a metal upper electrode 301, disposed in contact under the gate electrode 224. The memory point 34 further comprises a layer of electrical insulation 310, typically an oxide adapted to form a conductive filament. The upper electrode 301 will be chosen from a compatible metal for the formation of a conductive filament in the insulator 310. The electrode 301 may for example be made of Ti, TiN or TaN.
    The material of the insulating layer 310 may for example be HfCte. Other materials may be used for the insulating layer 310, among which, without limitation, the HfSiON or HfAlO (favorable to the performance of the memory point 34). The insulating layer 310 is formed on the gate insulating layer 223. The insulating layer 310 may for example have a thickness of between 1 and 10 nm, preferably of at most 5 nm, preferably of order of 1.5 nm. In general, the layer 310 will have a thickness and a suitable material, in a manner known per se, to allow the formation of a conductive filament of an OxRAM memory point.
    This embodiment makes it possible not to include a lower electrode of the memory point 34 in the gate stack 220, which makes it possible to avoid forming a screen for the electric field of the gate electrode 224 towards the zone of channel 203.
    The programming / deprogramming of the memory point 34, the switching of the transistor 2 and / or the reading of the programming state of the memory point 34 can be performed as detailed with reference to the fourth embodiment. In the absence of a lower electrode in contact with the insulator 310 of the memory point 34, it is not necessary to implement a current control for the programming.
    Figure 6 is a schematic sectional view of an integrated circuit 1 according to a fifth embodiment of the invention. The integrated circuit 1 according to this fifth embodiment is identical to that of the fourth embodiment, except the structure of the memory point 35.
    In this embodiment, the memory point 35 includes a metal upper electrode 301 disposed in contact beneath the gate electrode 224. The memory point 35 further includes an insulator layer 310 extending from the upper electrode 301. in contact with the gate insulator 223. The memory point 35 further includes lower electrodes 303 and 304 formed on the gate insulator 223, and separated from each other by the insulator layer. 310. The material of the lower electrodes 303 and 304 may be identical to that of the upper electrode 301.
    The electrodes 303 and 304 are connected to the control circuit 91, so as to be able to program or deprogram the memory point 35. The programming of the memory point 35 may, for example, induce the formation of filaments between the electrode 301 and the electrode 303. on the one hand, between the electrode 301 and the electrode 304 on the other hand, and / or between the electrodes 303 and 304, and / or between the electrode 301 and the doped zone 241.
    Although this embodiment has been described in the particular case of a FDSOI type transistor, the structure of the memory point 35 can also be adopted for a transistor 2 on a solid substrate and / or without a doped zone 241 in the zone of channel 203.
    To program the memory point 35, a filament can be formed between the electrode 301 and the electrode 303 by applying a suitable potential difference between these electrodes via the control circuit 91, a filament can be formed between the 301 electrode and the electrode 304 by applying a suitable potential difference between these electrodes through the control circuit 91, or form a filament between the electrodes 303 and 304 by applying a suitable potential difference between these electrodes by the intermediate of the control circuit 91.
    To suppress each of the conductive filaments and thus deprogram the memory point 35, the control circuit 91 can apply appropriate potential differences, with polarities opposite to those used for programming.
    The middle part of the insulator 310 present between the electrodes 303 and 304 makes it possible to limit the size of the screen formed by the electrodes 303 and 304 for the electric field of the gate electrode 224 towards the channel zone 203, while by favoring the programming and the deprogramming of the memory point 35.
    Figure 7 is a schematic sectional view of an integrated circuit 1 according to a sixth embodiment. The integrated circuit 1 according to this sixth embodiment differs from the integrated circuit of the third embodiment only in the structure of its gate stack 220. The gate stack 220 comprises a gate insulator 223 formed on the channel area 203. The gate stack 220 includes a RRAM memory point 3 using the gate insulator 223 to form the conductive filament. The RRAM memory point 3 comprises a metal upper electrode 301 formed in contact on the gate insulator 223. The gate stack 220 further comprises a polysilicon gate electrode 224 disposed in contact with the upper electrode 301 of the gate. memory 36. A contact layer 221 is disposed on the gate electrode 224 to provide protection and electrical isolation thereof. Electrical insulating spacers 231 and 232 are formed on the edges of the gate stack 220. The spacers 231, 232 cover the flanks of the gate insulator 223, the upper electrode 301, the gate electrode 224 and the contact layer 221. The spacers 231, 232 electrically isolate the gate electrode 224 and the upper electrode 301 from the source and drain contacts 211 and 212, respectively. The electrical contacts 211 and 212 are formed in contact respectively with the drain 201 and the source 202. The electrical contacts 211 and 212 are arranged on either side of the gate stack 220. The gate insulator 223 can example be realized in HfSiON. The thickness of the gate insulator 223 is typically between 1 and 5 nm.
    For forming the conductive filament and thus programming the memory point 36, the control circuit 91 applies a suitable programming potential difference between the upper electrode 301 on the one hand and the source contact 211 and / or the other on the other hand. drain 212.
    In the example illustrated, it is also possible to form the conductive filament of the memory point 36 by the application of a potential on an optional doped zone 241 formed in the channel zone 203.
    This embodiment provides a particularly simple structure, with a mode of programming / deprogramming also very simple.
    Figure 8 is a schematic sectional view of an integrated circuit 1 according to a seventh embodiment. The integrated circuit 1 according to this seventh embodiment is identical to that of the fourth embodiment, except the structure of the memory point 37. The memory point 37 here includes an insulating layer 310 extending from the gate insulator 223. until contact with the gate electrode 224. The memory point 37 further comprises upper electrodes 301 and 302 formed under the gate electrode 224. The upper electrodes 301 and 302 are separated from each other by the insulation layer 310.
    The electrodes 301 and 302 are connected to the control circuit 91, so that the memory point 37 can be programmed or deprogrammed. It is also conceivable for the electrodes 301 and 302 to be in electrical contact with the gate electrode 224, in order to program / deprogramming by means of a polarization of this gate electrode 224.
    The programming aims at forming a filament through the thickness of the insulator 310. The formation of such a filament is for example made by polarizing the electrodes 301 and 302 at a first potential, and simultaneously polarizing the zone 241, the contact 211 and / or the contact 212 at a second potential.
    This embodiment aims to limit the screen that could form the electrodes 301 and 302 for the field generated by the gate electrode 224 to the channel area 203.
    Figure 9 is a schematic sectional view of an integrated circuit 1 according to an eighth embodiment. The integrated circuit 1 according to this eighth embodiment differs from the integrated circuit of FIG. 8 by an overflow of the source 201 and the drain 202 in line with the gate insulator 223 (the channel region becoming narrower).
    This embodiment aims to promote the programming / deprogramming of the memory point 38 by applying a potential on the source 201 and / or the drain 202.
    Figure 10 is a schematic sectional view of an integrated circuit 1 according to a ninth embodiment. The integrated circuit 1 according to this ninth embodiment differs from the integrated circuit of FIG. 9 by the structure of the gate stack 220. The gate stack 220 comprises a gate insulator 223 formed on the channel zone 203. L gate stack 220 also comprises a polysilicon gate electrode 224 disposed in contact on memory point 39. A contact layer 221 is disposed on gate electrode 224 to ensure its connection. RRAM memory point 3 comprises a top electrode metal electrode 301 formed below the gate electrode 224. The upper metal electrode 301 is here formed on the side of the gate stack in contact with the spacer 231. The electrode 301 is separated from the spacer 232 by the intermediate of an insulation layer 310. The electrode 301 is separated from the gate insulator 223 via the insulating layer 310. The insulation layer 310 extends further to contact with the gate insulator 223. The memory point 39 further includes a lower metal electrode 303 formed on the drain 202 and isolated from the channel zone 203 through the gate insulator 223. The lower electrode 303 is here in contact with the spacer 232.
    The electrodes 301 and 303 can be connected to the control circuit 91 so that the memory point 39 can be programmed or deprogrammed, forming or removing a filament between these electrodes. The control circuit 91 can also apply respective potentials to the electrodes 301 and 303 via respectively the gate electrode 224 and the drain contact 212.
    Figure 11 is a schematic sectional view of an integrated circuit 1 according to a tenth embodiment of the invention. The integrated circuit 1 here comprises a field effect transistor 2 comprising a gate stack 220 and an active layer having a known structure of the state of the art.
    The field effect transistor 2 is here provided on a buried insulating layer 120. The active semiconductor layer of the field effect transistor 2 is thus electrically isolated from the substrate 100 via the insulating layer 120. The buried insulating layer 120 may for example be of UTBOX type (for Ultra Thin Burried Oxide in English language) and typically have a thickness of between 10 and 50 nanometers. The buried insulating layer 120 may for example be made in a manner known per se in SiO 2.
    A rear gate is here formed under the buried insulating layer 120. The rear gate is further used to form a memory point 41 under the active layer. For this purpose, the memory point 41 comprises a metal layer 420 formed on the substrate 100. The metal layer 420 may have a thickness and a composition identical to the electrode 301 detailed above. The memory point 41 further comprises an insulating layer 410 formed on the metal layer 420, and insulating the insulating layer 120 of the metal layer 420. The insulating layer 410 may have a thickness and a composition identical to the insulating layer 310 detailed above.
    To form the conductive filament and thus program the memory point 41, the control circuit 91 applies a suitable programming potential difference between the metal layer 420 forming an electrode of the memory point 41, and on the other hand the source 201 and / or the drain 202.
    To suppress the conductive filament and thus to deprogram the memory point 41, the control circuit 91 applies a suitable deprogramming potential difference between the metal layer 420 and the source 201 and / or the drain 202. The difference The potential for deprogramming is of opposite polarity to that of the programming potential difference.
    Depending on the programmed or deprogrammed state of the memory point 41, when the control circuit 91 applies a potential to the layer 420, the electric field applied to the channel zone 203 is different. Consequently, the threshold voltage of the transistor 2 is modified as a function of the programming state of the memory point 41. The association of the memory point 41 with the field effect transistor 2 can also be used: - to modulate the threshold voltage of transistor 2 by means of the programming state of memory point 41; or to allow reading of the programming state of the memory point 41 via the transistor 2.
    The programming of the memory point 41 generally requires a potential difference greater than that of a memory point of the gate stack 220. On the other hand, the memory point 41 has a better immunity than that of a memory point 31 to 39. in harsh environments, for example, electrostatic discharges (ESD for Electrostatic Discharge in English). In general, it may for example be envisaged that the programming potential difference for a memory point of the gate stack 220 will be of the order of 1V, whereas a programming potential difference for a memory point under a SOI insulation layer will be rather of the order of 4V, thus making the memory point more robust in applications facing potentially multiple external defects.
    Figure 12 is a schematic sectional view of an integrated circuit 1 according to an eleventh embodiment. The integrated circuit 1 according to this embodiment is identical to the integrated circuit of the tenth embodiment, except the structure of the memory point 42.
    The memory point 42 comprises an insulating layer 410 formed in contact under the insulating layer 120. The electrodes 421, 422 and 423 are respectively aligned under the source 201, the channel zone 203, and the drain 202. The electrodes 421, 422 and 423 are in contact with each other. with the substrate 100. The electrodes 421, 422 and 423 are separated from each other by the insulating layer 410, the insulating layer 410 extending between the electrodes 421, 422 and 423 until it contacts the substrate 100.
    Figure 13 is a schematic sectional view of an integrated circuit 1 according to a twelfth embodiment. The integrated circuit 1 according to this embodiment combines a memory point 312 included in the gate stack 220, and a memory point 43 formed under the active layer.
    This embodiment makes it possible to modulate the threshold voltage of transistor 2 with a very large amplitude.
    In this embodiment, the programming of the memory point 43 can also be performed by applying a potential difference between the electrode 420 and the zone 241, provided here in the channel zone 203.
    The control circuit 91 is advantageously configured to control the programming / deprogramming current of the memory points, to avoid inducing an accelerated alteration of these memory points during programming / deprogramming cycles.
    It is conceivable to make the control circuit 91 cointegrated with the circuit 1, or in the form of an external circuit connected by pins to the circuit 1.
    权利要求:
    Claims (16)
    [1" id="c-fr-0001]
    An integrated circuit (1), characterized in that it comprises: a field effect transistor (2), comprising: first and second conduction electrodes (201, 202); a channel region (203) disposed between the first and second conduction electrodes; a gate stack (220) disposed vertically above the channel region, and comprising a gate electrode (222); a RRAM type memory point (31, 41) arranged under the channel zone, or arranged in the gate stack beneath the gate electrode.
    [2" id="c-fr-0002]
    An integrated circuit (1) according to claim 1, comprising a programming circuit (91) configured to selectively create or remove a conductive filament in said memory point (31,41).
    [3" id="c-fr-0003]
    3. Integrated circuit (1) according to claim 1 or 2, wherein said memory point (31) is of type OxRAM.
    [4" id="c-fr-0004]
    4. Integrated circuit (1) according to any one of claims 1 to 3, wherein said memory point (31) is formed in the gate stack (222).
    [5" id="c-fr-0005]
    An integrated circuit (1) according to claim 4, wherein: said memory point (34) comprises a first electrode (301) in electrical contact with the gate electrode, and comprises an insulator (310) in contact with the first electrode and configured for selective formation of a conductive filament.
    [6" id="c-fr-0006]
    6. Integrated circuit (1) according to claims 2 and 4, wherein said transistor (2) is FDSOI type, the channel region (203) of said transistor having a region including a dopant implantation (241), said circuit programming (91) being configured to apply a potential difference between said first memory point electrode (301) and said dopant implantation region (241) so as to form a conductive filament in the insulator (310).
    [7" id="c-fr-0007]
    The integrated circuit (1) of claim 6, wherein said memory point insulator (223) is a gate insulator in contact with the channel region (203).
    [8" id="c-fr-0008]
    An integrated circuit (1) according to claims 2 and 4, wherein: said memory point (34) comprises a first electrode (301) in electrical contact with the gate electrode, and comprises an insulator (310) in contact with the first electrode and configured for selective formation of a conductive filament; said programming circuit (91) is configured to apply a potential difference between said first electrode (301) of the memory point and the first and / or the second conduction electrode (201, 202) of the transistor (2) so as to form a conductive filament in the insulation (310).
    [9" id="c-fr-0009]
    An integrated circuit according to claims 2 and 4, wherein: said transistor (2) comprises a gate insulator (223) in contact with the channel region (203); said memory point (35) comprises: a first electrode (301) in electrical contact with the gate electrode; an insulator (310) in contact with the first electrode (301) and configured for the selective formation of a conductive filament; a second electrode (303) formed in contact with said gate insulator (223), separated from said first electrode via the insulator (310) of the memory point (35); said programming circuit (91) is configured to apply a potential difference between said first electrode (301) of the memory point and the second electrode (303) of the memory point to form a conductive filament in the insulation (310) .
    [10" id="c-fr-0010]
    10. Integrated circuit (1) according to any one of claims 1 to 3, wherein said transistor (2) is SOI type and wherein the memory point (41) is provided under the channel zone (203).
    [11" id="c-fr-0011]
    11. The integrated circuit (1) according to claim 10, wherein said memory point (41) comprises: a first electrode (420) formed in a semiconductor substrate (100) directly above the channel zone (203); ); an insulator (410) in contact with the first electrode, separating the first electrode (420) from the channel region (203), and configured for the selective formation of a conductive filament.
    [12" id="c-fr-0012]
    The integrated circuit (1) according to claim 11, wherein said programming circuit (91) being configured to apply a potential difference between said first electrode (420) of the memory point (41) and the first and / or second conduction electrode (201, 202) of the transistor (2) so as to form a conductive filament in the insulator (410).
    [13" id="c-fr-0013]
    An integrated circuit (1) according to claim 11, wherein: the channel region (203) of said transistor has a region including dopant implantation (241); said programming circuit (91) is configured to apply a potential difference between said first electrode (420) of the memory point (43) and said region including the implantation of dopants (241) so as to form a conductive filament in the insulation (410).
    [14" id="c-fr-0014]
    The integrated circuit (1) of claim 10, wherein said memory point (42) comprises: at least two electrodes (421,422) in a semiconductor substrate (100) under the channel zone (203) ; an insulator (410) in contact with said at least two electrodes, separating the channel region (203) and said at least two electrodes (421, 422) formed in the semiconductor substrate, and configured for the selective formation of a filament driver.
    [15" id="c-fr-0015]
    The integrated circuit (1) according to any one of claims 5 to 9 or 11 to 14, wherein said first electrode (301) is formed of a metal selected from the group consisting of Ti, TiN and TaN.
    [16" id="c-fr-0016]
    An integrated circuit (1) according to any one of claims 5 to 9 or 11 to 15, wherein said insulator (310, 223) is formed of a material selected from the group consisting of HfCte, HfSiON or HfAIO.
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    同族专利:
    公开号 | 公开日
    US20170179196A1|2017-06-22|
    FR3045938B1|2018-03-09|
    US9831288B2|2017-11-28|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US20090212363A1|2008-02-27|2009-08-27|Advanced Micro Devices, Inc.|Method for forming a one-transistor memory cell and related structure|
    CN103021950A|2011-09-20|2013-04-03|复旦大学|Method for preparing embedded storage based on change-resistant gate medium|
    US20130119340A1|2011-11-15|2013-05-16|National Chiao Tung University|Multi-bit resistive-switching memory cell and array|
    EP2833410A2|2013-07-29|2015-02-04|Samsung Electronics Co., Ltd|Nonvolatile memory transistor, device including the same and method of operating the transistor|
    US20150262671A1|2014-03-13|2015-09-17|Kabushiki Kaisha Toshiba|Non-volatile memory device|
    US20150311257A1|2014-04-29|2015-10-29|Intermolecular Inc.|Resistive Random Access Memory Cells Having Shared Electrodes with Transistor Devices|FR3087290A1|2018-10-16|2020-04-17|Stmicroelectronics Sa|MEMORY POINT|EP1880409B1|2005-04-21|2014-03-26|Freescale Semiconductor, Inc.|Method of fabricating a mos device with a high-k or sion gate dielectric|
    US7626864B2|2006-04-26|2009-12-01|Chih-Hsin Wang|Electrically alterable non-volatile memory cells and arrays|
    US9230651B2|2012-04-08|2016-01-05|Zeno Semiconductor, Inc.|Memory device having electrically floating body transitor|
    US9741857B2|2015-08-07|2017-08-22|Ahmad Tarakji|Approach for an area-efficient and scalable CMOS performance based on advanced Silicon-On-Insulator , Silicon-On-Sapphire and Silicon-On-Nothing technologies|CN108389964B|2018-04-03|2021-05-25|集美大学|Method for preparing resistive random access memory by using nano shielding layer to perform ion positioning injection|
    US10374039B1|2018-04-25|2019-08-06|International Business Machines Corporation|Enhanced field bipolar resistive RAM integrated with FDSOI technology|
    US10580977B2|2018-07-24|2020-03-03|International Business Machines Corporation|Tightly integrated 1T1R ReRAM for planar technology|
    CN109545792B|2018-11-29|2022-01-04|上海华力微电子有限公司|SONOS storage structure and manufacturing method thereof|
    US11189661B2|2019-09-05|2021-11-30|International Business Machines Corporation|FinFET 2T2R RRAM|
    法律状态:
    2016-11-21| PLFP| Fee payment|Year of fee payment: 2 |
    2017-06-23| PLSC| Publication of the preliminary search report|Effective date: 20170623 |
    2017-11-21| PLFP| Fee payment|Year of fee payment: 3 |
    2019-12-30| PLFP| Fee payment|Year of fee payment: 5 |
    2020-12-28| PLFP| Fee payment|Year of fee payment: 6 |
    2021-12-31| PLFP| Fee payment|Year of fee payment: 7 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1563063A|FR3045938B1|2015-12-22|2015-12-22|INTEGRATED CIRCUIT COINTEGRATING A FET TRANSISTOR AND A RRAM MEMORY POINT|
    FR1563063|2015-12-22|FR1563063A| FR3045938B1|2015-12-22|2015-12-22|INTEGRATED CIRCUIT COINTEGRATING A FET TRANSISTOR AND A RRAM MEMORY POINT|
    US15/387,850| US9831288B2|2015-12-22|2016-12-22|Integrated circuit cointegrating a FET transistor and a RRAM memory point|
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